E1 Timers

The table below shows the timers used with the E1 component (0x01).

Timer ID

Description: (State Used); Timer Description

Default Value

(10 ms)

1

(S19) Incoming Layer 4 busy out Acknowledge wait

400

2

(S2) Incoming Stage 1 FWD digit receive wait

2000

3

(S3) Incoming Stage 2 FWD digit receive wait

2000

4

(S4) Incoming Stage 3 FWD digit receive wait

2000

5

(S5) Incoming Stage 4 FWD digit receive wait

2000

6

(S13) Layer 4 Connect wait

24,000

7

(S14) Layer 4 wait

400

8

(S21) Clear Forward (idle line signaling) wait

1500

9

(S3) Incoming Stage 2 Initial FWD digit receive wait

2000

10

(S2) Incoming Stage 1 Initial FWD digit receive wait

2000

11

(S5) Incoming Stage 4 Initial FWD digit receive wait

2000

12

(S4) Incoming Stage 3 Initial FWD digit receive wait

2000

13

(S15) Layer 3 Circuit Release wait

10

14

(S18) Layer 3 Circuit Release wait

10

15

(S6) Host Control Wait

6000

16

(S13) Layer 3 Connect wait

24000

17

(S29) Seize Acknowledge wait

400

18

(S31) Time to wait before transmitting idle signal after detecting glare

10

19

(S32) Time to wait before looking for idle signal after transmitting idle signal after detecting glare

10

20

(S39) Outgoing Stage 1 BWD R2 signal wait

1500

21

(S39) Outgoing Stage 1 Initial BWD R2 signal wait

1500

22

(S41) Outgoing Stage 2 BWD R2 signal wait

1500

23

(S41) Outgoing Stage 2 Initial BWD R2 signal wait

1500

24

(S43) Outgoing Stage 3 BWD R2 signal wait

1500

25

(S43) Outgoing Stage 3 Initial BWD R2 signal wait

1500

26

(S45) Outgoing Stage 4 BWD R2 signal wait

1500

27

(S45) Outgoing Stage 4 Initial BWD R2 signal wait

1500

28

(S46) Outgoing wait for answer

24000

29

(S48) Outgoing Layer 4 Clear wait

400

30

(S49) Outgoing idle line signal wait

12000

31

(S50) Outgoing idle line signal wait after glare detected

12000

32

(S24) Host Control wait

24000

33

(S33) Time to wait for Clear Forward after glare detected

1000

34

Receive line signaling filter

4

36

(S6, S24) Incoming BWD R2 Cycle Complete Event wait

400

38

(S10) Time to wait for idle line signaling after invalid line signal detected while receiving FWD R2 digits

2000

39

(S22) Layer 3 Clear Forward wait

300

40

(S39) Outgoing Stage 1 BWD A signal wait after sending all of Stage 1 FWD digits

2000

41

(S2, S3, S4, S5) FWD R2 digits receive wait when String Collection Data field in Inpulsing Parameters Configure is set to 0xFF

20

43

R2 Cycle Complete Event wait

200

45

(S43) Time to wait for next BWD R2 signal when stage 3 digits have been outpulsed

2000