Configuring clocking

The txcfg.txt clock command defines the clocking configuration of the TX board main clock source. This clock is used as the internal clock for TX boards. The clock signal can also be routed to other clocking signals. The clock source can be a clock signal of the H.100/H.110 bus, the TX board internal oscillator, or an oscillator or trunk connected to another device in the system (refer to H.100 and H.110 bus clocking overview).

If the clock command is not specified, the TX board remains in its default clocking mode (standalone mode). In this mode, the main clock source is the on-board oscillator. No clock signals are driven and clock fallback is disabled.

This topic presents:

• Clock command

• Configuring fallback

• Configuring NETREF

Clock command

The clocking configuration statement syntax is:

clock source [=network] outsigs [netref speed] [fallback source [=fallback network]]

where source specifies the source of the timing reference signal and is one of the following values:

where outsigs specifies the clock signal to drive and is one of the following values:

where netref speed optionally specifies the NETREF speed and is one of the following values:

where fallback source optionally specifies the clock signal to fall back to and is one of the following values:

Note: If fallback source is not specified, clock fallback is disabled on the board.

Configuring fallback

Primary clock master

Follow these guidelines when configuring a TX board as the primary clock master:

• Its primary timing reference must be a NETWORK reference. This timing reference can be any one of its T1/E1 trunks or the NETREF signal from the CT bus.

• Its fallback timing reference must be a different NETWORK reference.

• It must be configured to drive one of the CT bus clocks (A_CLOCK or B_CLOCK).

For example:

clock net=1 a - net=2

This clocking configuration receives the timing reference from network 1 clock, drives A_CLOCK, and falls back to network 2 clock.

Secondary clock master

Follow these guidelines when configuring a TX board as the secondary clock master:

• It must receive its primary timing reference from the CT bus clock driven by the primary clock master (either A_CLOCK or B_CLOCK).

• It must drive the CT bus clock not driven by the primary master. For example, if the primary clock master is driving A_CLOCK, the secondary clock master must drive B_CLOCK. In this case, both clocks are synchronized.

• It must have a fallback timing reference. This timing reference must not be the primary clock master's primary or fallback timing reference.

For example:

clock a b - net=1

This clocking configuration receives the timing reference from A_CLOCK, drives B_CLOCK, and falls back to network 1 clock.

Clock slave

Follow these guidelines when configuring a TX board as the clock slave:

• The primary clock source is the primary CT bus clock driven by the primary clock master.  

• The fallback clock source is the secondary CT bus clock driven by the secondary clock master.

For example:

clock a - - b

This clocking configuration receives the timing reference from A_CLOCK and falls back to B_CLOCK.

Configuring NETREF

Use the txcfg.txt netref command to route a clock signal recovered from a specified T1/E1 network connection to the indicated H.100/H.110 bus NETREF signals. If the netref command is not specified, the TX board does not drive any of the H.100/H.110 NETREF clock signals.

The NETREF clocking configuration statement syntax is:

netref network outsigs [netref speed]

where network is the network number (T1/E1 trunk number) from which to derive the clock signal, and outsigs specifies the clock signal to drive and is one of the following values:

where netref speed optionally specifies the NETREF speed and is one of the following values: